LM3S615-IQN50-C2

Product Summary

The LM3S615-IQN50-C2 microcontroller is based on the ARM Cortex M3 controller core operating at up to 50 MHz, with 32 kB flash and 8 kB SRAM. The LM3S615-IQN50-C2 also features real-time industrial connectivity, with an SSI / SPI controller, an I2C interface, and 2 UARTs. The LM3S615-IQN50-C2 microcontroller also features advanced motion control features, including 6 motion-control PWM outputs with dead-band and 1 fault protection inputs for low-latency shutdown. The LM3S615-IQN50-C2 microcontroller also features intelligent analog capability, including 3 analog comparators and 2 channels of highly accurate 10-bit analog-to-digital conversion - with the ability to sample at speeds of 500K samples per second. Finally, the LM3S615-IQN50-C2 microcontroller provides a 24-bit systick timer, 3 32-bit or 6 16-bit general-purpose timers, a watchdog timer, a low drop-out voltage regulator so that only one supply voltage is required, brown-out reset, power-on reset controller, and up to 34 GPIOs.

Parametrics

LM3S615-IQN50-C2 absolute maximum ratings: (1)VESDHBM: 2.0 kV; (2)VESDCDM: 1.0 kV; (3)VESDMM: 100 V.

Features

LM3S615-IQN50-C2 features: (1)System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism; (2)Thumb-compatible Thumb-2-only instruction set processor core for high code density; (3)50-MHz operation; (4)Hardware-division and single-cycle-multiplication; (5)Integrated Nested Vectored Interrupt Controller (NVIC)providing deterministic interrupt handling; (6)29 interrupts with eight priority levels; (7)Optimized for single-cycle flash usage; (8)Three sleep modes with clock gating for low power; (9)Single-cycle multiply instruction and hardware divide; (10)Atomic operations; (11)ARM Thumb2 mixed 16-/32-bit instruction set; (12)1.25 DMIPS/MHz.

Diagrams

<IMG border=0 alt="LM3S615-IQN50-C2 block diagram" src="http://www.seekic.com/uploadfile/ic-mfg/201282703527854.jpg">